12-bit 150MSPS Pipeline ADC

INNOSILICON Pipeline ADC IP is a 3.3V, 12-bit, 150Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input accepts single-ended or differential signals. The ADC is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies up to 70MHz, making it ideal for intermediate frequency (IF) sampling applications.

The ADC IP consumes only 160mW while delivering a typical 66dB signal-to-noise ratio (SNR) performance at a 70MHz input frequency. In addition to low operating power, the ADC features a few µW power-down mode to conserve power during idle periods.

A flexible reference structure allows the ADC IP to use its internal precision bandgap reference or accept an externally applied reference. The ADC provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

Analog-to-digital conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two's complement or Gray code. The output data has a simple timing interface for application. It is changed on the falling edge of clock and can be latched externally on the rising edge of clock.


  • 12-Bit A/D converter

  • Conversion rate > 150 MSPS

  • Power supply analog 3.3 V +/- 10%

  • Power supply analog 1.2 V - 1.32 V

  • Power supply digital 1.2 V +/- 10%

  • Power dissipation Pd = 150 mW (typical)

  • Temperature range (junction) -40 C to 120 C

  • Input signal nominal 1 Vdpp (differential pk-pk)

  • Input referred offset < +/- 10 mV

  • Input signal common-mode ~ 1.2 V

  • Integral Linearity Error +/- 2 LSB

  • Differential Linearity Error +/- 1 LSB

  • Input capacitance (each side) < 10 pF

  • SNR > 66 dBFS for 0 < Fin < 70 MHz

  • THD < -69 dB for 0 < Fin < 70 MHz

  • Spurious free dynamic range (SFDR) > 78 dBc

  • Spurious free dynamic range (30 MHz +/- 1 MHz) > 84 dBc

  • Power supply rejection ratio (PSRR) > 60 dB

  • Turn on/off time < 0.5 us

  • Output data 2’s complement format


  • Low power consumption

  • Fully customizable

  • Small area

  • Simple integration process



Mobile and wireless communication, multimedia Imaging and digital TV, Internet of Things (IOT), and sensor data acquisition application.