图形双倍数据速率 (GDDR) 是一种现代类型的同步图形随机存取存储器 (SGRAM),具有高带宽 DDR 接口,专为显卡、游戏机和高性能计算而设计。 GDDR 6和GDDR 6X 是目前带宽最高的 GDDR 内存解决方案,与 GDDR5 相比,能够支持更高的每引脚带宽(GDDR6X 高达 24Gbps,GDDR6 高达 16Gbps)、更低的工作电压(1.35V)、更高的性能和更低的功耗。

Innosilicon GDDR6 PHY 是世界上第一个经过芯片验证的商用 GDDR6内存接口IP,包含PHY IP和控制器controller IP,完全符合 JEDEC GDDR6 (JESD250) 标准,每个引脚支持高达 16Gbps。GDDR6 接口支持 2 个通道,每个通道 16 位,总数据宽度为 32 位。 Innosilicon GDDR6 PHY 每引脚速度高达 16Gbps,提供高达 64GB/s 的最大带宽。

Innosilicon GDDR6X IP 是世界上目前唯一经过芯片验证的商用 GDDR6X IP,包含PHY IP和控制器controller IP。Innosilicon GDDR6X PHY 使用四级脉冲幅度调制 (PAM4) 信号来提供高达84Gs的最大带宽,它采用14nm先进 FinFET 节点,以实现领先的客户集成。

用于 IP 核的 Innosilicon 系统感知设计方法提供了以客户为中心的体验,并具有快速的上市时间和一次性达标的质量。 Innosilicon 提供灵活的 IP 核交付,并直接与客户合作,提供完整的系统信号和电源完整性分析,优化芯片布局。最后,客户将收到一个带有全套测试软件的硬宏解决方案,用于快速启动和调试。

Graphics Double Data Rate (GDDR) is a modern type of Synchronous Graphics Random-Access Memory (SGRAM) with a high bandwidth DDR interface designed for use in graphics cards, game consoles, and high-performance computing. GDDR6/6X are currently the highest-bandwidth GDDR memory solutions, capable of supporting increased per-pin bandwidth (up to 24Gbps for GDDR6X, 16Gbps for GDDR6), lower operating voltages (1.35V), higher performance and lower power consumption compared to GDDR5/GDDR5X.

The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, which is fully compliant with the JEDEC GDDR6 (JESD250) standard, supporting up to 16Gbps per pin. The GDDR6 interface supports 2 channels, each with 16bits for a total data width of 32bits. With speed up to 16Gbps per pin, the Innosilicon GDDR6 PHY offers a maximum bandwidth of up to 64GB/s. And, the Innosilicon GDDR6X PHY uses four-level pulse amplitude modulation (PAM4) signaling to extract more efficiency and higher data rates, which will be available in advanced FinFET nodes for leading-edge customer integration.

The Innosilicon system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with customers to provide a full system signal and power integrity analysis to create an optimized chip layout. In the end, the customer will receive a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.


  • Data rate up to 24Gbps for GDDR6X, 16Gbps for GDDR6

  • PAM4 (only for GDDR6X) and POD-135 compatible signaling

  • Supports both quad data rate (QDR) and double data rate (DDR) data (WCK) mode

  • Driver strength and on-die termination (ODT) auto calibration

  • Supports both Write and Read CRC

  • Per-bit TX and RX data phase adjustment

  • Internal high-performance low-jitter PLL

  • Supports both hardware and software training including WCK2CK training, command training, read training and write training

  • Dynamic eye-diagram training for Write and Read operation

  • TX de-emphasis EQ and RX DFE EQ to improve signal integrity

  • Internal VREF with DFE for data inputs, with receiver characteristics programmable per pin

  • Data bus inversion (DBI) and CA bus inversion (CABI)

  • Supports EDC full rate and half rate hold pattern, programmable EDC tracking bandwidth

  • Various low power modes


  • World’s first silicon-proven commercial GDDR6/6X IP

  • All major processes fully covered, such as 110nm, 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.

  • JEDEC JESD250 standard compliant (GDDR6)

  • Offers leading performance, power, and area per terabit

  • Optional PI/SI and thermal co-design service

  • Full support from IP delivery to production